A logic LSI which is manufactured by a master slice method, is a device wherein a desired logical function is realized in such a way that semiconductor elements, e. g., MISFETs (Metal Insulator Semiconductor Field Effect Transistors) constituting basic cells and I/O (input/output) cells are formed on a semiconductor substrate beforehand, and that the semiconductor elements are thereafter interconnected by wiring in accordance with logical specifications.
With such a logic LSI of the master slice method, predetermined numbers of bonding pads and underlying layers (semiconductor elements) for the I/O cells are manufactured on the semiconductor substrate beforehand irrespective of the number of pins which are to be actually used, and hence, pins which are not to be used arise in some logical specifications. In the ensuing description, such unused pins as are not connected to the internal circuits of the semiconductor substrate shall be called "NC (Non-Connected) pins".